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INTEGRATED CIRCUITS
74LVC86 Quad 2-input EXCLUSIVE-OR gate
Product specification Supersedes data of February 1996 IC24 Data Handbook 1997 Mar 18
Philips Semiconductors
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74LVC86
FEATURES
* Wide supply voltage range of 1.2 to 3.6 V * In accordance with JEDEC standard no. 8-1A. * Inputs accept voltages up to 5.5 V * CMOS low power consumption * Direct interface with TTL levels
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr = tf 2.5 ns SYMBOL tPHL tPLH CI CPD PARAMETER Propagation delay nA, nB to nY Input capacitance Power dissipation capacitance per gate
DESCRIPTION
The 74LVC86 is a high-performance, low-power, low-voltage Si-gate CMOS device that is pin and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V/5 V environment. The 74LVC86 provides the 2-input EXCLUSIVE-OR function.
CONDITIONS CL = 15 pF; VCC = 3.3 V VCC = 3.3 V, VI = GND to VCC1
TYPICAL 3.7 5.0 55
UNIT ns pF pF
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi ) (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES 14-Pin Plastic DIL 14-Pin Plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74LVC86 N 74LVC86 D 74LVC86 DB 74LVC86 PW NORTH AMERICA 74LVC86 N 74LVC86 D 74LVC86 DB 74LVC86PW DH PKG. DWG. # SOT27-1 SOT108-1 SOT337-1 SOT402-1
PIN CONFIGURATION
1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4B 4A 4Y 3B 3A 3Y
LOGIC SYMBOL (IEEE/IEC)
1 2 =1 3
4 5
=1
6
9 10
=1
8
12
SV00481
13
=1
11
PIN DESCRIPTION
PIN NUMBER 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 SYMBOL 1A - 4A 1B - 4B 1Y - 4Y GND VCC Data inputs Data inputs Data outputs Ground (0 V) Positive supply voltage FUNCTION
SV00479
1997 Mar 18
2
853-1946 17864
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74LVC86
LOGIC SYMBOL
1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 2Y 3Y 4Y 3 6 8 11
FUNCTION TABLE
INPUTS nA L L H H
SV00480
OUTPUTS nB L H L H nY L H H L
LOGIC DIAGRAM (ONE GATE)
A Y B
NOTES: H = HIGH voltage level L = LOW voltage level
SV00478
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VCC VI VI/O VO Tamb tr, tf PARAMETER DC supply voltage (for max. speed performance) DC supply voltage (for low-voltage applications) DC input voltage range DC input voltage range for I/Os DC output voltage range Operating free-air temperature range Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS LIMITS MIN 2.7 1.2 0 0 0 -40 0 0 MAX 3.6 3.6 5.5 VCC VCC +85 20 10 UNIT V V V V V C ns/V
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL VCC IIK VI VI/O IOK VOUT IOUT IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC input voltage range for I/Os DC output diode current DC output voltage DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VO uVCC or VO t 0 Note 2 VO = 0 to VCC VI t 0 Note 2 CONDITIONS RATING -0.5 to +6.5 -50 -0.5 to +5.5 -0.5 to VCC +0.5 "50 -0.5 to VCC +0.5 "50 "100 -60 to +150 500 500 UNIT V mA V V mA V mA mA C
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1997 Mar 18
3
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74LVC86
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIH HIGH level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V VCC = 1.2V VCC = 2.7 to 3.6V VCC = 2.7V; VI = VIH or VIL; IO = -12mA VO OH HIGH level output voltage VCC = 3.0V; VI = VIH or VIL; IO = -100A VCC = 3.0V; VI = VIH or VIL; IO = -12mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100A VCC = 3.0V; VI = VIH or VIL; IO = 24mA II IIHZ/IILZ IOZ ICC ICC Input leakage current Input current for common I/O pins 3-State output OFF-state current Quiescent supply current Additional quiescent supply current per input pin VCC = 3 6V; VI = 5 5V or GND 3.6V; 5.5V VCC = 3.6V; VI = VCC or GND VCC = 3.6V; VI = VIH or VIL; VO = VCC or GND VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V; IO = 0 Not for I/O pins "0 1 "0.1 "0.1 0.1 0.1 5 GND VCC*0.5 VCC*0.2 VCC*0.6 VCC*1.0 0.40 0.20 0.55 "5 "15 "10 20 500 A A A A A V VCC V VCC 2.0 GND 0.8 V TYP1 MAX V UNIT
VIL
LOW level Input voltage
NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
AC CHARACTERISTICS
GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF; RL = 500W; Tamb = -40_C to +85_C LIMITS SYMBOL tPHL/ tPLH PARAMETER Propagation delay nA, nB to nY WAVEFORM VCC = 3.3V 0.3V MIN Figures 1, 2 1.5 TYP1 4.0 MAX 6.5 MIN 1.5 VCC = 2.7V TYP1 4.5 MAX 7.0 VCC = 1.2V TYP 20 ns UNIT
NOTE: 1. These typical values are at VCC = 3.3V and Tamb = 25C.
AC WAVEFORMS
VM = 1.5 V at VCC 2.7 V; VM = 0.5 at VCC < 2.7 V; VOL and VOH are the typical output voltage drop that occur with the output load.
VI nA, nB INPUT GND t PHL VOH nY OUTPUT VOL VM t PLH VM
TEST CIRCUIT
VCC S1 2 < VCC Open GND
PULSE GENERATOR
VI D.U.T. RT
VO
500
CL
50pF
500
Test
S1 Open 2 < VCC GND
SV00477
VCC t 2.7V 2.7V - 3.6V
VI VCC 2.7V
tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
Figure 1. Input (nA, nB) to output (nY) propagation delays
SY00003
Figure 2. Load circuitry for switching times.
1997 Mar 18
4
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74LVC86
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
1997 Mar 18
5
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74LVC86
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
1997 Mar 18
6
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74LVC86
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
1997 Mar 18
7
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74LVC86
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
1997 Mar 18
8
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74LVC86
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A.
Philips Semiconductors
1997 Mar 18 9

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